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? semiconductor components industries, llc, 2002 june, 2002 rev. 3 1 publication order number: mc74lvxt8053/d mc74lvxt8053 analog multiplexer / demultiplexer highperformance silicongate cmos the mc74lvxt8053 utilizes silicongate cmos technology to achieve fast propagation delays, low on resistances, and low off leakage currents. this analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from v cc to gnd). the lvxt8053 is similar in pinout to the highspeed hc4053a, and the metalgate mc14053b. the channelselect inputs determine which one of the analog inputs/outputs is to be connected by means of an analog switch to the common output/input. when the enable pin is high, all analog switches are turned off. the channelselect and enable inputs are compatible with ttltype input thresholds. the input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logiclevel translator from 3.0 v cmos logic to 5.0 v cmos logic or from 1.8 v cmos logic to 3.0 v cmos logic while operating at the highervoltage power supply. the mc74lvxt8053 input structure provides protection when voltages up to 7v are applied, regardless of the supply voltage. this allows the mc74lvxt8053 to be used to interface 5 v circuits to 3 v circuits. this device has been designed so that the on resistance (r on ) is more linear over input voltage than r on of metalgate cmos analog switches. ? fast switching and propagation speeds ? low crosstalk between switches ? diode protection on all inputs/outputs ? analog power supply range (v cc gnd) = 2.0 v to 6.0 v ? digital (control) power supply range (v cc gnd) = 2.0 v to 6.0 v ? improved linearity and lower on resistance than metalgate counterparts ? low noise ? in compliance with the requirements of jedec standard no. 7a logic diagram triple singlepole, doubleposition plus common off x0 12 x1 13 a 11 b 10 c 9 enable 6 x switch y switch x 14 analog inputs/outputs channelselect inputs pin 16 = v cc pin 8 = gnd common outputs/inputs y0 2 y1 1 y 15 z0 5 z1 3 z 4 z switch note: this device allows independent control of each switch. channelselect input a controls the xswitch, input b controls the yswitch and input c controls the zswitch 16lead soic d suffix case 751b 16lead tssop dt suffix case 948f pin connection and marking diagram (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 y x x1 x0 a b c y1 y0 z1 z z0 enable nc gnd l l l l h h h h x l l h h l l h h x l h l h l h l h x function table mc74lvxt8053 control inputs on channels enable select cba l l l l l l l l h x = don't care z0 z0 z0 z0 z1 z1 z1 z1 y0 y0 y1 y1 y0 y0 y1 y1 x0 x1 x0 x1 x0 x1 x0 x1 none for detailed package marking information, see the marking diagram section on page 10 of this data sheet. device package shipping ordering information mc74lvxt8053dr2 soic 2500 units/reel mc74lvxt8053dt tssop 96 units/rail mc74lvxt8053dtr2 tssop 2500 units/reel http://onsemi.com
mc74lvxt8053 http://onsemi.com 2 ??????????????????????? ??????????????????????? maximum ratings* ???? ???? symbol ?????????????? ?????????????? parameter ????? ????? value ??? ??? unit ???? ???? v cc ?????????????? ?????????????? positive dc supply voltage (referenced to gnd) ????? ????? 0.5 to + 7.0 ??? ??? v ???? ???? v is ?????????????? ?????????????? analog input voltage ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? v in ?????????????? ?????????????? digital input voltage (referenced to gnd) ????? ????? 0.5 to v cc + 0.5 ??? ??? v ???? ???? i ?????????????? ?????????????? dc current, into or out of any pin ????? ????? 20 ??? ??? ma ???? ? ?? ? ???? p d ?????????????? ? ???????????? ? ?????????????? power dissipation in still air, soic package2 tssop package2 ????? ? ??? ? ????? 500 450 ??? ? ? ? ??? mw ???? ???? t stg ?????????????? ?????????????? storage temperature range ????? ????? 65 to + 150 ??? ??? c ???? ???? t l ?????????????? ?????????????? lead temperature, 1 mm from case for 10 seconds ????? ????? 260 ??? ??? c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. 2derating soic package: 7 mw/ c from 65 c to 125 c tssop package: 6.1 mw/ c from 65 c to 125 c recommended operating conditions ???? ???? symbol ??????????????? ??????????????? parameter ??? ??? min ?? ?? max ??? ??? unit ???? ???? v cc ??????????????? ??????????????? positive dc supply voltage (referenced to gnd) ??? ??? 2.0 ?? ?? 6.0 ??? ??? v ???? ???? v is ??????????????? ??????????????? analog input voltage ??? ??? 0.0 ?? ?? v cc ??? ??? v ???? ???? v in ??????????????? ??????????????? digital input voltage (referenced to gnd) ??? ??? gnd ?? ?? v cc ??? ??? v ???? ???? v io * ??????????????? ??????????????? static or dynamic voltage across switch ??? ??? ?? ?? 1.2 ??? ??? v ???? ???? t a ??????????????? ??????????????? operating temperature range, all package types ??? ??? 55 ?? ?? + 85 ??? ??? c ???? ? ?? ? ? ?? ? ???? t r , t f ??????????????? ? ????????????? ? ? ????????????? ? ??????????????? input rise/fall time (channel select or enable inputs) v cc = 3.3 v 0.3 v v cc = 5.0 v 0.5 v ??? ? ? ? ? ? ? ??? 0 0 ?? ?? ?? ?? 100 20 ??? ? ? ? ? ? ? ??? ns/v *for voltage drops across switch greater than 1.2 v (switch on), excessive v cc current may be drawn; i.e., the current out of the switch may contain both v cc and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded. dc characteristics digital section (voltages referenced to gnd) v cc guaranteed limit symbol parameter condition v cc v 55 to 25 c 85 c 125 c unit v ih minimum highlevel input voltage, channelselect or enable inputs r on = per spec 3.0 4.5 5.5 1.2 2.0 2.0 1.2 2.0 2.0 1.2 2.0 2.0 v v il maximum lowlevel input voltage, channelselect or enable inputs r on = per spec 3.0 4.5 5.5 0.53 0.8 0.8 0.53 0.8 0.8 0.53 0.8 0.8 v i in maximum input leakage current, channelselect or enable inputs v in = v cc or gnd, 5.5 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) channel select, enable and v is = v cc or gnd; v io = 0 v 5.5 4 40 160 a this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74lvxt8053 http://onsemi.com 3 dc electrical characteristics analog section ???? ???? ????????? ????????? ?????????? ?????????? ??? ??? ?????????? ?????????? guaranteed limit ?? ?? ???? ???? symbol ????????? ????????? parameter ?????????? ?????????? test conditions ??? ??? v cc v ???? ???? 55 to 25 c ???? ???? 85 c ???? ???? 125 c ?? ?? unit ???? ? ?? ? ???? r on ????????? ? ??????? ? ????????? maximum aono resistance ?????????? ? ???????? ? ?????????? v in = v il or v ih v is = v cc to gnd |i s | 10.0 ma (figures 1, 2) ??? ? ? ? ??? 3.0 4.5 5.5 ???? ? ?? ? ???? 40 30 25 ???? ? ?? ? ???? 45 32 28 ???? ? ?? ? ???? 50 37 30 ?? ?? ?? ???? ? ?? ? ? ?? ? ???? ????????? ? ??????? ? ? ??????? ? ????????? ?????????? ? ???????? ? ? ???????? ? ?????????? v in = v il or v ih v is = v cc or gnd (endpoints) |i s | 10.0 ma (figures 1, 2) ??? ? ? ? ? ? ? ??? 3.0 4.5 5.5 ???? ? ?? ? ? ?? ? ???? 30 25 20 ???? ? ?? ? ? ?? ? ???? 35 28 25 ???? ? ?? ? ? ?? ? ???? 40 35 30 ?? ?? ?? ?? ???? ? ?? ? ???? r on ????????? ? ??????? ? ????????? maximum difference in aono resistance between any two channels in the same package ?????????? ? ???????? ? ?????????? v in = v il or v ih v is = 1/2 (v cc gnd) |i s | 10.0 ma ??? ? ? ? ??? 3.0 4.5 5.5 ???? ? ?? ? ???? 15 8.0 8.0 ???? ? ?? ? ???? 20 12 12 ???? ? ?? ? ???? 25 15 15 ?? ?? ?? i off maximum offchannel leakage current, any one channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 3) 5.5 0.1 0.5 1.0 a maximum offchannel leakage current, common channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 4) 5.5 0.1 1.0 2.0 i on maximum onchannel leakage current, channeltochannel v in = v il or v ih ; switchtoswitch = v cc or gnd; (figure 5) 5.5 0.1 1.0 2.0 a ac characteristics (c l = 50 pf, input t r = t f = 3 ns) v cc guaranteed limit symbol parameter v cc v 55 to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, channelselect to analog output (figure 9) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns t plh , t phl maximum propagation delay, analog input to analog output (figure 10) 2.0 3.0 4.5 5.5 4.0 3.0 1.0 1.0 6.0 5.0 2.0 2.0 8.0 6.0 2.0 2.0 ns t plz , t phz maximum propagation delay, enable to analog output (figure 11) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns t pzl , t pzh maximum propagation delay, enable to analog output (figure 11) 2.0 3.0 4.5 5.5 20 12 8.0 8.0 25 14 10 10 30 15 12 12 ns c in maximum input capacitance, channelselect or enable inputs 10 10 10 pf c i/o maximum capacitance analog i/o 35 35 35 pf (all switches off) common o/i 50 50 50 feedthrough 1.0 1.0 1.0 c pd typical @ 25 c, v cc = 5.0 v pf power dissipation capacitance (figure 13)* 45 * used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74lvxt8053 http://onsemi.com 4 additional application characteristics (gnd = 0 v) v cc limit* symbol parameter condition v cc v 25 c unit bw maximum onchannel bandwidth or mi i f r f in = 1mhz sine wave; adjust f in voltage to obtain 0dbm at v if f u til db m t r d 3 db mh minimum frequency response (figure 6) v os ; increase f in frequency until db meter reads 3 db; r l = 50 , c l = 10 pf 3.0 4.5 5.5 120 120 120 z offchannel feedthrough isolation (figure 7) f in = sine wave; adjust f in voltage to obtain 0 dbm at v is f in = 10khz, r l = 600 , c l = 50 pf 3.0 4.5 5.5 50 50 50 db f in = 1.0mhz, r l = 50 , c l = 10pf 3.0 4.5 5.5 37 37 37 feedthrough noise. channelselect input to common i/o (figure 8) v in 1mhz square wave (t r = t f = 3 ns); adjust r l at setup so that i s = 0a; enable = gnd r l = 600 , c l = 50pf 3.0 4.5 5.5 25 105 135 mv pp r l = 10 k , c l = 10pf 3.0 4.5 5.5 35 145 190 crosstalk between any two switches (figure 12) f in = sine wave; adjust f in voltage to obtain 0dbm at v is f in = 10 khz, r l = 600 , c l = 50pf 3.0 4.5 5.5 50 50 50 db f in = 1.0mhz, r l = 50 , c l = 10pf 3.0 4.5 5.5 60 60 60 thd total harmonic distortion (figure 14) f in = 1khz, r l = 10 k , c l = 50pf thd = thd measured thd source v is = 2.0v pp sine wave v is = 4.0v pp sine wave v is = 5.0v pp sine wave 3.0 4.5 5.5 0.10 0.08 0.05 % *limits not tested. determined by design and verified by qualification. figure 1a. typical on resistance, v cc = 3.0 v 25 20 15 10 5 0 1.0 2.0 3.0 4.0 v in , input voltage (volts) r on , on resistance (ohms) 85 c -55 c 125 c 0 25 c 40 35 30 45
mc74lvxt8053 http://onsemi.com 5 figure 1b. typical on resistance, v cc = 4.5 v figure 1c. typical on resistance, v cc = 5.5 v 25 20 5 0 1.0 2.0 4.0 3.0 5.0 v in , input voltage (volts) r on , on resistance (ohms) 85 c -55 c 125 c 0 25 c 5 0 1.0 2.0 3.0 4.0 5.0 6.0 v in , input voltage (volts) r on , on resistance (ohms) 85 c -55 c 125 c 0 25 c 10 15 30 10 15 20 25 30 35 figure 1. on resistance test setup plotter mini computer programmable power supply dc analyzer v cc device under test + - gnd analog in common out gnd
mc74lvxt8053 http://onsemi.com 6 figure 2. maximum off channel leakage current, any one channel, test setup figure 3. maximum off channel leakage current, common channel, test setup figure 4. maximum on channel leakage current, channel to channel, test setup figure 5. maximum on channel bandwidth, test setup figure 6. off channel feedthrough isolation, test setup figure 7. feedthrough noise, channel select to common out, test setup off off 6 8 16 common o/i v cc v ih nc a v cc gnd v cc off off 6 8 16 common o/i v cc v ih analog i/o v cc gnd v cc on off 6 8 16 common o/i v cc v il v cc gnd v cc n/c a analog i/o on 6 8 16 v cc 0.1 f c l * f in r l db meter *includes all probe and jig capacitance off 6 8 16 v cc 0.1 f c l * f in r l db meter *includes all probe and jig capacitance v os v os r l v is v il or v ih channel select on/off 6 8 16 v cc c l * r l *includes all probe and jig capacitance channel select test point common o/i 11 v cc off/on analog i/o r l r l v ih v il v in 1 mhz t r = t f = 3 ns
mc74lvxt8053 http://onsemi.com 7 figure 9a. propagation delays, channel select to analog out figure 9b. propagation delay, test setup channel select to analog out figure 10a. propagation delays, analog in to analog out figure 10b. propagation delay, test setup analog in to analog out figure 11a. propagation delays, enable to analog out figure 11b. propagation delay, test setup enable to analog out v cc gnd channel select analog out 50% t plh t phl 50% on/off 6 8 16 v cc c l * *includes all probe and jig capacitance channel select test point common o/i off/on analog i/o v cc v cc gnd analog in analog out 50% t plh t phl 50% on 6 8 16 v cc c l * *includes all probe and jig capacitance test point common o/i analog i/o on/off 6 8 enable v cc enable 90% 50% 10% t f t r v cc gnd analog out t pzl analog out t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% analog i/o c l * test point 16 v cc 1k 1 2 1 2 position 1 when testing t phz and t pzh position 2 when testing t plz and t pzl v ih v il
mc74lvxt8053 http://onsemi.com 8 r l figure 12. crosstalk between any two switches, test setup figure 13. power dissipation capacitance, test setup figure 14a. total harmonic distortion, test setup figure 14b. plot, harmonic distortion 0 -10 -20 -30 -40 -50 -100 1.0 2.0 3.125 frequency (khz) db -60 -70 -80 -90 fundamental frequency device source on 6 8 16 c l * *includes all probe and jig capacitance off r l r l v is r l c l * v os f in 0.1 f on/off 6 8 16 v cc channel select nc common o/i off/on analog i/o v cc a 11 v cc on 6 8 16 v cc 0.1 f c l * f in r l to distortion meter *includes all probe and jig capacitance v os v is applications information the channel select and enable control pins should be at v cc or gnd logic levels. v cc being recognized as a logic high and gnd being recognized as a logic low. in this example: v cc = +5v = logic high gnd = 0v = logic low the maximum analog voltage swing is determined by the supply voltages v cc . the positive peak analog voltage should not exceed v cc . similarly, the negative peak analog voltage should not go below gnd. in this example, the difference between v cc and gnd is five volts. therefore, using the configuration of figure 15, a maximum analog signal of five volts peaktopeak can be controlled. unused analog inputs/outputs may be left floating (i.e., not connected). however, tying unused analog inputs and outputs to v cc or gnd through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. although used here, balanced supplies are not a requirement. the only constraints on the power supplies are that: v cc gnd = 2 to 6 volts when voltage transients above v cc and/or below gnd are anticipated on the analog channels, external germanium or schottky diodes (d x ) are recommended as shown in figure 16. these diodes should be able to absorb the maximum anticipated current surges during clipping.
mc74lvxt8053 http://onsemi.com 9 analog signal figure 15. application example figure 16. external germanium or schottky clipping diodes a. low voltage logic level shifting control b. 2stage logic level shifting control figure 17. interfacing low voltage cmos inputs on 6 8 16 +5v analog signal +5v 0v +5v 0v 11 10 9 to external lsttl compatible circuitry 0 to v ih digital signals on/off 8 16 v cc gnd d x v cc d x gnd d x v cc d x analog signal on/off 6 8 16 +3v analog signal +3v gnd +3v gnd 11 10 9 1.8 - 2.5v circuitry analog signal on/off 6 8 16 +5v analog signal +5v gnd +5v gnd 11 10 9 1.8 - 2.5v circuitry 1.8 - 2.5v mc74vhc1gt50 buffers v cc = 3.0v figure 18. function diagram, lvxt8053 13 x1 12 x0 1 y1 2 y0 3 z1 5 z0 14 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable 15 y 4 z
mc74lvxt8053 http://onsemi.com 10 15 16 14 13 12 11 10 2 1 34567 9 8 marking diagrams (top view) 15 16 14 13 12 11 10 2 1 34567 9 8 16lead soic d suffix case 751b 16lead tssop dt suffix case 948f lvxt8051 lvxt awlyww* 8051 alyw* *see applications note #and8004/d for date code and traceability information.
mc74lvxt8053 http://onsemi.com 11 package dimensions 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m d suffix plastic soic package case 751b05 issue j
mc74lvxt8053 http://onsemi.com 12 package dimensions dt suffix plastic tssop package case 948f01 issue o ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74lvxt8053/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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